HardCopy® IV ASIC I/O pins have the same basic I/O structures as their Stratix® IV FPGA companion, delivering system-level performance and flexibility required to communicate with a multitude of devices. Intellectual property (IP) cores, and software tools such as TimeQuest timing analyzer, simultaneous switching noise (SSN) estimator, and pin planner all aid in ease of use and rapid integration.
Table 1. HardCopy IV ASIC I/O Connectivity Overview |
|
Feature |
Details |
LVDS Support on All I/O Banks |
|
DDR Support on All I/O Banks |
|
Independent Banks |
|
Differential Signaling
HardCopy IV ASIC I/O pins support high-performance, DC-coupled LVDS transmit and receive channels on the side I/O banks with additional lower speed LVDS support on the top and bottom banks. Every high-speed, side I/O LVDS pair has a hard dynamic phase alignment (DPA) block to eliminate clock-to-channel and channel-to-channel skew, as shown in Figure 1. HardCopy IV ASIC high-speed LVDS I/O pins support interface standards such as SPI-4.2, SFI-4.1, SGMII, UTOPIA IV, 10 GbE XSBI, the RapidIO® standard, and SerialLite.
The HardCopy IV ASIC high-speed LVDS feature supports the following:
- Hard DPA block with serializer/deserializer (SERDES) and clock-forwarding capability for soft-CDR
- Programmable pre-emphasis and Voltage Output Differential (VOD)
- Differential on-chip termination (OCT)
For more information on differential signaling see the High-Speed Differential I/O Interfaces with DPA in HardCopy IV Devices (PDF) chapter of the HardCopy IV Device Handbook.
Single-Ended I/O Support
The HardCopy IV ASIC single-ended I/O feature supports the following:
- Programmable slew rate and drive strength
- Dynamic trace compensation (variable delay chains for board trace mismatch compensation on both input and output signals)
- Serial, parallel, and dynamic on-chip termination (OCT)
For more information on OCT, see the HardCopy IV Device I/O Features (PDF) chapter of the HardCopy IV Devices Handbook.
HardCopy IV ASIC I/O pins support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X (see Table 2).
Table 2. HardCopy IV ASIC Differential and Single Ended I/O Support |
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I/O Standards |
Performance Target (1) |
Typical Application |
Comments |
Differential I/O |
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LVDS |
1.25 Gbps |
Chip-to-chip |
OCT |
Differential HSTL |
350 MHz |
Memory |
OCT |
Differential SSTL |
350 MHz |
Memory |
OCT |
LVPECL |
300 MHz |
General purpose |
Clock inputs only |
Single-Ended I/O |
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3.0-V/2.5-V/1.8-V LVTTL |
167 MHz |
General purpose |
Impedance matching |
3.0-V/2.5-V/1.8-V/1.5-V/1.2-V LVCMOS |
167 MHz |
General purpose |
Impedance matching |
SSTL-2 Class I and II |
200 MHz |
Memory |
Serial and parallel OCT |
SSTL-15 Class I and II |
533 MHz |
Memory |
Serial and parallel OCT |
SSTL-18 Class I and II |
333 MHz |
Memory |
Serial and parallel OCT |
1.8-V/1.5V/1.2-V HSTL I and II |
350 MHz |
Memory |
Serial and parallel OCT |
3.0-V PCI |
66 MHz |
PC, embedded |
Impedance matching |
3.0-V PCI-X 1.0 |
133 MHz |
PC, embedded |
Impedance matching |
- Pending characterization
For more information on I/O standards, see the HardCopy IV Device I/O Features (PDF) chapter of the HardCopy IV Device Handbook.
High-Speed External Memory Interfaces
HardCopy IV ASIC I/O pins support existing and emerging external memory standards such as DDR, DDR2, DDR3, QDR II, QDR II+, and RLDRAMII at frequencies up to 400 MHz (see Table 3). A self-calibrating datapath takes advantage of the new I/O structure, dynamically adjusting itself to always provide the highest reliable frequency of operation across process, voltage, and temperature.
The HardCopy IV ASIC external memory interfaces feature supports the following:
- SDR and half data rate (HDR–half the frequency and twice the data width of SDR) input and output options
- HDR block with alignment and synchronization
- De-skew, read/write leveling and clock-domain crossing functionality
Table 3. HardCopy IV ASIC External Memory Interface Performance (1) |
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Memory Standard |
I/O Standard |
Maximum Clock Speed (MHz) |
Maximum Data Rate (Mbps) |
DDR SDRAM |
SSTL-2 |
200 |
400 |
DDR2 SDRAM |
SSTL-1.8 |
333 |
667 |
DDR3 |
SSTL-1.5 |
533 |
1,067 |
QDR II |
1.8-V/1.5-V HSTL |
300 |
1,200 |
QDR II + |
1.8-V/1.5-V HSTL |
350 |
1,400 |
RLDRAMII |
1.8-V HSTL |
400 |
800 |
- Pending characterization
For more information on external memory interfaces on HardCopy IV ASICs, see Altera's External Memory Solution Center and the External Memory Interfaces in HardCopy IV Devices (PDF) chapter of the HardCopy IV Device Handbook.
Signal Integrity
HardCopy IV ASIC I/O banks deliver best-in-class signal integrity, low SSN, and superior eye quality through many chip-level and package-level enhancements.
The HardCopy IV ASIC signal integrity I/O feature supports the following:
- 8:1:1 User I/O to power/ground ratio
- Optimized signal return paths
- Staggered output delay control
- Optimized on-die and on-package decoupling
