Altera® transceivers have a proven track record of meeting system bandwidth, power, and bit-error rate (BER) requirements. The technology leadership continues with the transceivers in our 28-nm Stratix® V FPGAs.
Stratix V FPGAs feature up to 66 full-duplex transceiver channels, with transceivers at data rates from 14.1 Gbps to 28.05 Gbps. Providing up to over 930 Gbps of transceiver bandwidth, Stratix V FPGAs deliver the highest system bandwidth at the lowest power consumption for a wide range of applications and protocols. In addition, the transceivers are compliant with a range of protocols and are equipped with a variety of signal conditioning features to support backplane, optical module, and chip-to-chip applications.
Building on its predecessor, Stratix V FPGA transceivers come with many enhancements for flexibility and robustness:
- Integration of on-die instrumentation
- Additional low-jitter LC transmit phase-locked loops (PLLs)
- Robust analog receive clock data recovery (CDR)
- Advanced transmit and receive equalization for backplane support at up to 14.1 Gbps
The transceivers also include full-featured embedded physical coding sublayer (PCS) hard intellectual property (IP) to simplify design, lower power, and save valuable core resources.
Each Stratix V FPGA transceiver channel consists of the physical media attachment (PMA), PCS, and hardened IP blocks with added clocking flexibilities and more independent channels. Every channel has a full PMA and PCS along with a dedicated independent receive analog PLL CDR. You'll have access to an abundant number of transmit clocking sources, including the wide data range support of the clock multiplication unit (CMU) as well as the low-jitter LC transmit PLLs.
Minimize the number of off-chip crystal oscillators by utilizing the new fractional PLLs (fPLLs) with precise frequency synthesis. Not only can the fPLLs generate fractional multiples of a reference clock, they can also be used to drive the transceiver reference clock.
Figure 1. Stratix V FPGA Transceiver Channel Components
Transceiver PMA
The flexible PMA is designed to be compliant across a wide range of protocols and mediums. Advanced equalization, on-die instrumentation, and partial reconfiguration are just some of the many PMA features offered on Stratix V FPGA transceivers. See Table 1 for more on PMA features and capabilities.
| Table 1. Transceiver PMA Features | |
| Features | Capability |
|---|---|
| Backplane, chip-to-chip, and chip-to-module support at up to 14.1 Gbps | Stratix V GX and GS FPGAs |
| Chip-to-chip and chip-to-module support at up to 28.05 Gbps | Stratix V GT FPGAs |
| Optical module support with electronic dispersion compensation (EDC) | XFP, SFP+, QSFP, CXP, CFP |
| Cable driving support | PCI Express® cable and eSATA applications |
| Continuous-time linear equalization (CTLE) | Receiver 4-stage linear equalization to support high-attenuation channels |
| Decision feedback equalization (DFE) | Receiver 5-tap digital equalizer to minimize losses and crosstalk |
| Adaptive equalization (ADCE) | Adaptive engine to automatically adjust equalization to compensate for changes over time |
| Analog PLL-based clock recovery | Superior jitter tolerance versus phase interpolation techniques |
| Programmable deserialization and word alignment | Flexible deserialization width and configurable word alignment patterns |
| Transmit equalization (pre-emphasis) | Transmit driver 4-tap pre-emphasis and de-emphasis for protocol compliance under lossy conditions |
| Ring and LC oscillator transmit PLLs | Choice of transmit PLLs per channel, optimized for specific protocols and applications |
| On-die instrumentation (EyeQ data-eye monitor) | Allows non-intrusive on-chip monitoring of both width and height of data eye |
| Dynamic and partial reconfiguration | Allows reconfiguration of single channels and the core on the fly, while other portions of the design are still running |
| Protocol support | Compliance with over 50 industry-standard protocols in the range of 14.1 Gbps to 28 Gbps |
Transceiver PCS
The Stratix V FPGA core logic connects to the PCS via an 8-, 10-, 16-, 20-, 32-, 40-, 64-, or 66-bit interface, depending on the transceiver data rate and protocol. Stratix V FPGAs contain PCS hard IP blocks to support PCI Express Gen3, Gen2, and Gen1, 40G/100G Ethernet, Interlaken, 10-Gbps Ethernet, XAUI, GbE, Serial RapidIO®, CPRI, 10G Basic (up to 14.1 Gbps), 6G Basic (up to 8.5 Gbps), and 3G Basic (up to 3.75 Gbps). Figure 2 details some of the main building blocks in the PCS to support the broad range of protocols.
Figure 2. PCS Building Blocks
Related Links
- Stratix V FPGAs
- HardCopy V ASICs
- Transceiver protocol
- Transceiver portfolio
- Read the Extending Transceiver Leadership at 28 nm (PDF) white paper
- Download the Transceiver Architecture in Stratix V Devices (PDF) chapter of the Stratix V device handbook
- Watch the Stratix V FPGA transceiver webcast
