A CPLD designer is defined to be a hardware engineer targeting a CPLD (for example, a MAX® II device).
Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.
| Table Legend | |
| Required if no prior experience | |
| Optional | |
| Suggested | |
| Instructor-Led / Virtual Classroom Training | ||
|---|---|---|
| Best Practices for Maximizing FPGA Design Productivity (IPRO200) (16 hours) |
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| Introduction to VHDL (IHDL110) (8 hours) |
or | Introduction to Verilog HDL (IHDL120) (8 hours) |
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| The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours) |
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| Advanced VHDL Design Techniques (IHDL240) (8 hours) |
or | Advanced Verilog HDL Design Techniques (IHDL230) (8 hours) |
