Embedded Systems - IP Cores

An intellectual property (IP) block, or an IP core, is a predesigned module that can be used in other designs. IP cores are to hardware design what libraries are to computer programming.

Altera University Program IP cores were developed to enhance the use of our development and education boards. They provide easy access to board peripherals. They can be included in user designs through the SOPC Builder. They are available in an open-source format with complete documentation, and are distributed as part of the University Program Installer.

Altera also provides numerous other IP cores, which are available at the Altera IP MegaStore™. The Altera-developed IP cores may be provided at no charge to qualified research projects at universities. Please contact university@altera.com for more information.

The University Program IP Cores were designed for the SOPC Builder software and cannot be used with the new Quartus II system integration tool, Qsys.

The University Program IP Cores are listed in the table below. They are avalable for different versions of Quartus II. Use the filters below to choose the appropriate cores.

Legacy University Program IP cores for older versions of the Quartus II software can be found here.