The Qsys interconnect components support the Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interfaces and are essential cores for system design. All components are provided at no charge and are considered Qsys Compliant.
The use of Altera’s Qsys and SOPC Builder components, intellectual property cores, and reference designs is governed by, and subject to, the terms and conditions of the Altera Program License Subscription Agreement, the Altera MegaCore Function License Terms and Conditions, and the Altera Hardware Reference Design License Agreement respectively.



