EDA Partners

The Altera^® Commitment to Cooperative Engineering Solutions (ACCESS) program ensures that you have a complete design solution in designing, verifying, and integrating Altera FPGAs and HardCopy^® ASICs into your systems.

List of ACCESS Program Partner Solutions By:

System-level design
Design creation
Synthesis
Simulation
Verification
Board-level design
ASIC prototyping

ACCESS Program Partner	System- Level Design	Design Creation	Synthesis	Simulation	Verification	Board-Level Design	ASIC Prototyping
Aldec, Inc.
Agilent Technologies
Agnisys Technology Pvt Ltd
Altium
Auspy Development Inc.
Blue Pearl
Bluespec
Cadence Design Systems,Inc.
Duolog Technologies
EMA Design Automation
FishTail
GateRocket
Impulse Accelerated Technologies
Mentor Graphics
NEC
PDTi
Poseidon Design Systems
Real Intent
Sigasi
Signal Integrity Software, Inc. (SiSoft)
Simucad Design Automation
SpringSoft Inc.
Symphony EDA
SynaptiCAD
Synopsys
Temento Systems
TransEDA
Zuken

*Table 1. System-Level Design*
EDA Vendor	Product Name	Design Solution
Altium	Altium Designer	High-level design tool
Agnisys Technology Pvt Ltd	IDesignSpec	Register map management
Bluespec	Bluespec Compiler	High-level synthesis
Cadence Design Systems,Inc.	C-to-Silicon Compiler	High-level synthesis
Duolog Technologies	Socrates	Register map management
Impulse Accelerated Technologies	ImpulseC CoDeveloper	High-level synthesis and simulation
Mentor Graphics	Catapult-C	High-level synthesis
NEC	CyberWorkBench	High-level synthesis
PDTi	SpectaReg	Register map management
Poseidon Design Systems	Triton Tuner	System-level simulation
Poseidon Design Systems	Triton Builder	High-level synthesis
SynaptiCAD	TestBencher Pro	High-level design tool
Synopsys	Synplify DSP	High-level design tool

*Table 2. Design Creation*
EDA Vendor	Product Name	Design Solution
Mentor Graphics	HDL Designer	Project management, design entry, and analysis tool
Sigasi	Sigasi HDT	Design entry, code comprehension, project management, and collaboration

*Table 3. Synthesis*
EDA Vendor	Product Name	Design Solution
Mentor Graphics	Precision RTL	Logic synthesis
	Precision RTL Plus	Advanced logic synthesis
	Precision Physical	Timing closure tool
Synopsys	Synplify Pro	Logic synthesis tool
Synopsys	Synplify Premier	Timing closure tool

*Table 4. Simulation*
EDA Vendor	Product Name	Design Solution
Aldec, Inc.	Aldec Active-HDL	Simulation
Aldec, Inc.	Aldec Riviera-PRO	Simulation
Cadence Design Systems,Inc.	Incisive Enterprise Simulator	Simulation
Mentor Graphics	ModelSim	Simulation
Mentor Graphics	Questa	Simulation
Simucad Design Automation	SILOS	Simulation
Symphony EDA	VHDL Simili	Simulation
SynaptiCAD	VeriLogger	Simulation
Synopsys	VCS	Simulation

*Table 5. Verification*
EDA Vendor	Product Name	Design Solution
Aldec, Inc.	ALINT	Register transfer level (RTL) checker
Blue Pearl	Indigo RTL Analysis	RTL checker
	Cobalt Timing Constraints Generation	Constraints generator
	Azure Constraints Validation	Constraints validation
Cadence Design Systems,Inc.	Encounter Conformal Equivalence Checker	Formal verification
EMA Design Automation	TimingDesigner	Timing verification
FishTail	Focus	Constraints generator
	Confirm	Timing-exception verification
	ReConfirm	Timing-exception validation
GateRocket	RocketDrive	Functional verification
GateRocket	RocketVision	Functional verification
Mentor Graphics	Formal Pro	Equivalence checking
	0-In Formal Verification	Functional verification
	0-In CDC	Clock domain crossing verification
Real Intent	Meridian	Clock domain crossing verification
SpringSoft Inc.	ProtoLink Probe Visualizer	Integrated RTL debug for FPGA prototype board
SynaptiCAD	TestBencher Pro	Testbench generator
SynaptiCAD	WaveFormer Pro	Timing verification
Synopsys	LEDA	RTL checker
	Identify and Indentify Pro	Integrated RTL debug
	Magellan	Functional verification
	Formality	Formal verification
Temento Systems	Dialite – Platform Edition	In-system verification and integrated RTL debug
Temento Systems	AMBA Bus Trace Analyzer	In-system verification
TransEDA	VN-Spec	Specification checker
	VN-Check	RTL checker
	VN-Cover	Finite state machine (FSM) coverage tool
	Coverability Analysis	Code coverage tool for simulation and testbench generation
	Assertain-HDL	RTL checker for simulation coverage
	Assertain-ABV	RTL checker for functional verification coverage

*Table 6. Board-Level Design*
EDA Vendor	Product Name	Design Solution
Agilent Technologies	Advanced Design System (ADS)	Signal integrity (SI) analysis
Altium	Altium Designer	PCB board schematics and layout SI analysis
Cadence Design Systems,Inc.	Allegro FPGA System Planner	FPGA I/O planning
	OrCAD FPGA System Planner	FPGA I/O planning
	Allegro PCB SI	SI analysis
	OrCAD Signal Explorer	SI analysis
	Allegro Design Entry HDL Allegro Design Entry CIS	PCB board schematics
	Cadence OrCAD Capture and Capture CIS	PCB board schematics
	Allegro PCB Design	PCB board layout
	OrCAD PCB Designer	PCB board layout
Mentor Graphics	I/O Designer	FPGA I/O planning
	HyperLynx SI	SI analysis
	DxDesigner	PCB board schematics
	PADS	PCB board schematics and layout
	Expedition Enterprise	PCB board layout
	Board Station	PCB board layout
Signal Integrity Software, Inc. (SiSoft)	Quantum-SI	SI analysis
Synopsys	HSPICE	SI analysis
Zuken	CR-5000	PCB board schematics and layout

*Table 7. ASIC Prototyping*
EDA Vendor	Product Name	Design Solution
Auspy Development Inc.	Auspy Partition System II	Multi-chip partitioning system
Synopsys	Certify	Multi-chip partitioning system

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EDA Partners

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