Altera provides extensive documentation and support for the Triple Speed Ethernet MegaCore® function to help you quickly and easily develop and debug Ethernet applications such as line cards, NIC cards, and switches operating at 10/100 megabits per second (Mbps) for fast Ethernet or 1000 Mbps for Gbps Ethernet.
Literature
- Triple-Speed Ethernet MegaCore Function User Guide (PDF)
- MegaCore IP Library Release Notes and Errata (PDF)
- Archive of intellectual property release notes
- Archive of intellectual property errata sheets
Application Notes
- AN 440: Accelerating Nios® II Networking Applications (PDF)
- AN 477: Designing RGMII Interfaces with FPGAs and HardCopy® ASICs (PDF)
- AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs (PDF)
- AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench (PDF)
- AN 633: Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and
GX Transceiver (PDF) - AN 647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design (PDF)
Reference Designs
- Triple-Speed Ethernet reference design for Stratix® IV GX device
- Triple-Speed Ethernet reference design for Arria® II GX device
Design Examples
- TSE: Constraint RGMII interface of Triple Speed Ethernet with the external PHY delay feature
- TSE: Instantiate TSE with external ALTGX / ALTLVDS
- TSE: Implement reset sequence in TSE Using ALTLVDS as transceiver
- TSE: Implement reset sequence in TSE using ALTGX as transceiver
Altera Knowledge Database
The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding the Triple Speed Ethernet MegaCore function.
See frequently viewed solutions:
- Why does fitting error occur for Triple Speed Ethernet IP MegaCore in the Cyclone® IV GX device?
- Why don't reset_rx_clk and reset_tx_clk signals of PCS-only variant and PCS-plus-PMA variant of Triple Speed Ethernet IP MegaCore synchronize to rx_clk and tx_clk?
- Why do Triple Speed Ethernet IP MegaCore instance’s transmit and receive phase-locked loop (PLL) for LVDS I/O fail to share the PLL?
- Why do multiple Triple Speed Ethernet IP MegaCore instances with LVDS I/O fail to share the same PLL?
- Why do multiple Triple Speed Ethernet IP MegaCore instances with transceivers fail to fit into the same transceiver Quadrant?
- Why is Triple Speed Ethernet IP MegaCore Physical Coding Sub-layer (PCS) register unable to read or write through the Avalon Memory Map (MM) Interface when the LED Link indicates link down?
Find additional solutions on theTriple Speed Ethernet MegaCore function.
Online Training Courses
- 10/100/1000-megabytes (MB) Ethernet design with Altera transceiver devices
- Chinese version: 10/100/1000-MB Ethernet design with Stratix IV GX FPGAs
Development Kits
The following development kits are available for the Triple Speed Ethernet MegaCore function:
- Arria II GX FPGA Development Kit
- Cyclone III FPGA Development Kit
- PCI Express®-based Development Kit, Stratix II GX Edition
- Stratix III FPGA Development Kit
- Stratix IV GX FPGA Development Kit
