Altera is an active member of the IEEE 802.3ba task force and is a leader in providing solutions for 40G and 100G Ethernet protocols. Altera® Stratix® V FPGAs with integrated transceivers are capable of running at 14.1 Gbps and provide a complete integrated solution for a 40G and 100G Ethernet protocol stack. This includes the multi-lane distribution (MLD) and physical coding sublayer (PCS) for the 40G and 100G protocol.
Stratix V GT FPGAs provide a fully integrated 10G/40G/100G-compliant solution for high-performance applications, utilizing built-in 28.05-Gbps transceivers along with hardened MLD and 64/66 PCS blocks to implement the entire 100G protocol stack in a single device. Table 1 provides an overview of the complete 100G solution.
| Table 1. Complete 100G Solution | |
| Solution | Description |
|---|---|
| Transceiver | Integrated 10GBASE-R-compliant transceivers |
| Supported data rates | 600 Mbps to 14.1 Gbps |
| Hardened intellectual property (IP) core | MLD and 64/66 PCS (compliant with 802.3ba) |
| Transceiver characterization report | Contact your local Altera sales representative |
Stratix V FPGA Technology Background
Altera's Stratix V GT devices are equipped with built-in transceivers that provide a dedicated mode for implementing the CAUI or XLAUI interface and allow the integration of multiple PHYs and 100G MACs into a single FPGA. Embedded within the transceivers are dedicated rate-matching FIFO buffers, 8B/10B and 64B/66B encoding and decoding functions, MLD, and word-alignment functions. Each group of three channels also has built-in channel alignment circuitry to minimize skew across the interface. Figure 1 shows the 100-Gbps Ethernet (100GbE) MAC with integrated PCS block diagram. Every transceiver channel has its own independent 64B/66B PCS blocks to support the 10GBASE-R protocol.
Figure 1. 100GbE MAC with Hardened MLD, 64B/66B PCS Blocks
Stratix V GT FPGA transceivers are architected to meet all the IEEE 802.3ae and IEEE 802.3ba specifications. These transceivers do not require any external EDC component to interface with a SFP+ optical module and are capable of driving a 10G backplane.
