Reduce System Costs by Integrating PCI Interface Functions

Many of today’s peripheral component interconnect (PCI) bus interfaces are implemented using an ASSP. However, the most common functions of PCI target interfaces can be implemented using CPLDs (example shown Figure 1), resulting in cost savings, added flexibility, and potential reductions in board space use. These benefits are readily available via complete, easy-to-use PCI interface solutions.

Figure 1: MAX II CPLD-Based PCI Interface Block Diagram

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