28-nm Stratix® V FPGAs simplify the challenges of designing for signal integrity by providing transceivers with best-in-class jitter and noise isolation. Advanced features in the transceivers simplify PCB design. Adaptive linear equalization and decision feedback equalization (DFE), multi-tap pre-emphasis, and the EyeQ eye viewer (see Table 1) all help compensate for inevitable board losses. There are also features that enhance the Stratix V FPGA die and package, resulting in excellent signal and power integrity and maximum user flexibility (see Table 2).
Plug & Play Signal Integrity
Stratix series FPGAs are the only devices in the industry that can:
- Automatically and continuously monitor and set the receive equalizer to the best eye opening (see Figure 1) for a particular high-speed interconnect.
- Provide Plug & Play Signal Integrity, as seen on Stratix II GX FPGAs in this video.
Our adaptive dispersion compensation engine (ADCE) technology, along with hot-socketing capability, allows you to load just one FPGA image for all card slots in your system. This reduces inventory, characterization, and factory test costs. ADCE in production can continuously monitor and compensate for manufacturing variations as well as process, voltage, and temperature (PVT) effects.
| Table 1. Signal Integrity Features of Stratix V Transceiver FPGAs | ||
| Feature | Specification | Benefits |
|---|---|---|
| EyeQ Eye Viewer | 32 horizontal steps 64 vertical steps |
|
| Programmable Receive Linear Equalization |
20-dB 4-stage filter |
|
| DFE With Auto-Adaptation | 5-tap | Helps mitigate crosstalk on lossy mediums (backplane) |
| Electronic Dispersion | Compensation for SFP+ | Full compliance (SR and LR) for SFP+; external electronic dispersion compensation (EDC) chip not needed |
| LC Transmit Phase-Locked Loop (PLL) | 3.25 Gbps – 12.5 Gbps; 20 Gbps - 28 Gbps | Sub picoseconds transmit output jitter helps achieve best eye opening and system bit error rate (BER) performance |
| Pre-Emphasis and Programmable VOD | 3-taps and Vod = 400 mV to 1,400 mV |
Dynamically programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis levels to compensate for pre-cursor and post-cursor inter-symbol interference (ISI) |
| On-Chip Regulators | Tx, Rx PLLs | On-die power supply regulators for transmitter and receiver PLL charge pump and voltage-controlled oscillator (VCO) provide superior noise immunity |
Significant architectural enhancements in the I/O blocks have increased overall external memory performance. Table 2 shows the proven I/O and packaging technology in Stratix V FPGAs.
- All timing-critical circuits in the DDR read-and-write paths are hardened in the I/O block to enable timing closure at 800 MHz.
- I/Os include on-chip dynamic termination to reduce the number of external components and minimize reflections.
- On-die capacitance (ODC) and on-package decoupling (OPD) capacitors suppress noise on the power lines, reducing noise coupling into the I/Os.
- Memory banks are isolated to prevent core noise from coupling to the outputs to provide optimal signal integrity.
| Table 2. I/O and Packaging Features for Optimal Signal Integrity | |
| Features | Benefits |
|---|---|
| 8:1:1 User I/O, Ground, and Power Ratio | Provides low impedance return path for every I/O channel to reduce loop inductance and noise. |
| Optimized Die- and Package-Level Signal Return Path | Optimizes return path with low impedance to reduce loop inductance and noise. |
| Adjustable Slew Rate Control | Controls signal edge rate to reduce noise. |
| Staggered Output Delay Control | Spaces out simultaneous switching outputs (SSO) switching time to reduce simultaneous switching noise (SSN). |
| Dynamic On-Chip Termination | Dynamically controls on-chip termination for proper line termination and impedance matching, which helps prevent reflections on the transmission line. Eliminates the need for external termination resistors to lower system cost and simplify PCB design. |
| On-Package and On-Die Decoupling | Provides high-frequency decoupling and suppresses power noise. Reduces the number of external PCB decoupling capacitors to lower system cost and simplify PCB design. |
Table 3 highlights the features and benefits of the high-speed differential signals of Stratix V FPGAs.
| Table 3. High-Speed Differential Signaling | |
| Features | Benefits |
|---|---|
| LVDS Buffer Enhancement | Includes programmable pre-emphasis and programmable VOD features to compensate for signal attenuation. |
| Dynamic Phase Alignment (DPA) | Compensates for skew in board layout, allowing source-synchronous I/Os to operate at higher data rates, which increases the likelihood of successful PCB layout. |
| Soft-CDR | Soft-CDR circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clocks at data rates up to 1.6 Gbps (including SGMII, Gigabit Ethernet, etc.) |
